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DE1-SoC RISC-V CPU

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High Level Diagram of SystemVerilog CPU + Memory
High Level Diagram of SystemVerilog CPU + Memory
By Alvin Li
1 min read

As part of my computer engineering coursework, I programmed a RISC-V CPU capable of carrying out basic Assembly instructions in a text file format. All parts of the CPU, including the ALU, registers, datapath, shifter, and finite state machine (FSM), were programmed using SystemVerilog inside Quartus. Testbenches and debugging through the waveform generator was done on Intel ModelSim. This project can be found on my Github: DE1-SoC RISC-V CPU

Verilog FPGA
This post is licensed under CC BY 4.0 by the author.